1. Field of the Invention
Embodiments of the invention relate to a display device and a method for driving the same.
2. Discussion of the Related Art
An active matrix liquid crystal display displays a motion picture using a thin film transistor (TFT) as a switching element. The active matrix liquid crystal display may be made to be smaller and more compact than a cathode ray tube (CRT) and thus may be applied to display units of portable information appliances, office equipments, computers, etc. Further, the active matrix liquid crystal display may be applied to televisions and thus is rapidly replacing the cathode ray tube.
A liquid crystal display includes a plurality of source driver integrated circuits (ICs) for supplying a data voltage to data lines of a liquid crystal display panel, a plurality of gate driver ICs for sequentially supplying a gate pulse (or a scan pulse) to gate lines of the liquid crystal display panel, a timing controller for controlling the source driver ICs and the gate driver ICs, etc.
The timing controller supplies digital video data, clocks for sampling of the digital video data, a control signal for controlling operations of the source driver ICs, etc. to the source driver ICs through an interface, for example, a mini low voltage differential signaling (LVDS) interface. The source driver ICs convert the digital video data received from the timing controller into an analog data voltage and supplies the analog data voltage to the data lines.
When the timing controller is connected to the source driver ICs in a multidrop manner through the mini LVDS interface, red (R) data transmission lines, green (G) data transmission lines, blue (B) data transmission lines, control lines for controlling operation timings of an output and a polarity conversion operation of the source driver ICs, clock transmission lines, etc are required between the timing controller and the source driver ICs. In the mini LVDS interface, RGB data, for example, RGB digital video data and a clock are transmitted as differential signal pair. Therefore, when odd data and even data are simultaneously transmitted, at least 14 lines are required between the timing controller and the source driver ICs for the transmission of the RGB data. When the RGB data is 10 bits, 18 lines are required. Thus, many lines has to be formed on a source printed circuit board (PCB) mounted between the timing controller and the source driver ICs. Hence, it is difficult to reduce a width of the source PCB.
A new signal transmission protocol (hereinafter referred to as “an EPI (clock Embedded Point-to-point Interface) protocol”) for connecting the timing controller and the source driver ICs in a point-to-point manner to minimize the number of lines between the timing controller and the source driver ICs and to stabilize the signal transmission was disclosed in U.S. Pat. No. 8,330,699 (issued Dec. 11, 2012), U.S. Pat. No. 7,898,518 (issued Mar. 1, 2011), and U.S. Pat. No. 7,948,465 (issued May 24, 2011) corresponding to the present applicant, and which are hereby incorporated by reference in their entirety.
The EPI protocol satisfies the following interface regulations (1) to (3).
(1) A transmitting terminal of the timing controller is connected to receiving terminals of the source driver ICs via data line pairs in a point-to-point manner.
(2) Separate clock line pairs are not connected between the timing controller and the source driver ICs. The timing controller transmits video data and control data along with a clock signal to the source driver ICs through the data line pairs.
(3) A clock recovery circuit for clock and data recovery (CDR) is embedded in each of the source driver ICs. The timing controller transmits a clock training pattern signal or a preamble signal to the source driver ICs, so that an output phase and an output frequency of the clock recovery circuit should be locked. After the output phase of the clock recovery circuit embedded in each source driver IC is locked, the clock recovery circuit generates an internal clock when the clock training pattern signal and the clock signal are input through the data line pairs.
When a phase and a frequency of the internal clock are locked, the source driver ICs feedback-input a lock signal of a high logic level indicating an output stabilization state to the timing controller. The lock signal is feedback-input to the timing controller through a lock feedback signal line connected to the timing controller and the last source driver IC.
When the phase and the frequency of the internal clock are stably locked, the clock recovery circuit of each source driver IC and the timing controller form a data link. The timing controller starts to transmit the video data and the control data to the source driver ICs in response to the lock signal received from the last source driver IC.
When the output phase and the output frequency of the clock recovery circuit embedded in even one of the source driver ICs are unlocked, the lock signal is inverted to a low logic level. The last source driver IC transmits the lock signal of the low logic level to the timing controller. In this instance, the timing controller retransmits the clock training pattern signal to all the source driver ICs and resumes clock training of the source driver ICs.
The EPI protocol is configured as a plurality of control data packets each having a predetermined length including a plurality of control informations for controlling the source driver ICs. An amount of control information included in one control data packet is limited. Thus, when one control data packet includes the control information exceeding its limited amount, the number of control data packets transmitted to the source driver ICs increases.
The control data packet is transmitted during a horizontal blank period. The horizontal blank period is a very short time, in which there is no data, between an Nth horizontal period, in which Nth line data is written to pixels of an Nth line of the display panel, and an (N+1)th horizontal period, in which (N+1)th line data is written to pixels of an (N+1)th line of the display panel, where N is a positive integer. When a sum of the lengths of the plurality of control data packets increases, a horizontal blank margin is lack. Hence, an image displayed on the display panel may be distorted, or erroneous operations of the source driver ICs may be caused.